An example of multi-stage amplifiers are low-dropout (LDO) regulators which are linear voltage regulators that can operate with relatively small input-output differential voltages. A typical LDO regulator 100 is illustrated in FIG. 1a. The LDO regulator 100 comprises an output stage 103, which comprises e.g. a field-effect transistor (FET), at the output, and a differential amplification stage or a differential amplifier 101 (also referred to as an error amplifier) at the input. A first input (fb) 107 of the differential amplifier 101 receives a fraction of the output voltage Vout determined by the voltage divider 104 comprising resistors R0 and R1. The second input (ref) to the differential amplifier 101 may be a stable voltage reference Vref 108 (also referred to as the bandgap reference). If the output voltage Vout changes relative to the reference voltage Vref, the drive voltage to the output stage, e.g. the power FET, changes by a feedback mechanism called main feedback loop to maintain a constant output voltage Vout.
The LDO regulator 100 of FIG. 1a further comprises an optional additional intermediate amplification stage 102 configured to amplify the output voltage of the differential amplification stage 101. As such, an intermediate amplification stage 102 may be used to provide an additional gain within the amplification path. Furthermore, the intermediate amplification stage 102 may provide a phase inversion.
In addition, the LDO regulator 100 may comprise an output capacitance Cout (also referred to as an output capacitor or a stabilization capacitor or a bybass capacitor) 105 parallel to the load 106. The output capacitor 105 is used to stabilize the output voltage Vout subject to a change of the load 106, in particular subject to a change of the load current Iload. It should be noted that typically the output current Iout at the output of the output stage 103 corresponds to the load current Iload through the load 106 of the regulator 100 (apart from typically minor currents through the voltage divider 104 and the output capacitance 105). Consequently, the terms output current Iout and load current Iload are used synonymously, if not specified otherwise.
Typically, it is desirable to provide a stable output voltage Vout, even subject to transients of the load 106. By way of example, the regulator 100 may be used to provide a stable output voltage Vout to the processor of an electronic device (such as a smartphone). The load current Iload may vary significantly between a sleep state and an active state of the processor, thereby varying the load 106 of the regulator 100. In order to ensure a reliable operation of the processor, the output voltage Vout should remain stable, even in response to such load transients.
At the same time, the LDO regulator 100 should be able to react rapidly to load transients, i.e. the LDO regulator 100 should be able to rapidly provide the requested load current Iload, subject to a load transient. This means that the LDO regulator 100 should exhibit a high bandwidth.
In this context, it is desirable to allow for a stable operation of the LDO regulator 100 with a large range of bypass capacitors 105 (e.g. from 200 nF up to 100 μF). Furthermore, it is desirable to reduce the die-size of the LDO regulator 100, while at the same time ensuring a stable operation of the LDO regulator 100 in a large range of frequencies. In addition, it is desirable to provide an improved power supply rejection ratio (PSRR) of the LDO regulator 100.